1. Field Of The Invention
The present invention relates generally to the field of digital data processing apparatus, hereinafter referred to simply as processors, and relates specifically to the timing or clock portion of such processors which times the operation of the other processor portions. More specifically, the invention relates to the clock generator of such clock portions which responds to the output of the associated clock oscillator or master clock of the clock portion to produce one or more clock phase signals which, in turn, do the actual timing of the operation of the other processor portions.
2. Description Of The Prior Art
The known forms of the above-noted clock generators, as used in the known processors, are usually of the multiphase type, that is, of the type wherein the generator produces a set of two or more of the above-noted clock phase signals within the processor. Accordingly, the present description will be directed to such multiphase generators.
Within the known processors embodying multiphase clock generators, the clock phase signals, which will be referred to hereinafter simply as clock signals, are distributed among the portions, circuits, or devices of the processor which require clocking or timing. Such portions will be referred to hereinafter simply as the timed portions of the processor. The number of clock signals which the generator produces in a given processor, and the manner in which such signals are utilized, are dictated by the nature of that processor.
Each of the clock signals in a typical processor consists of a series of timing or clock pulses, and the pulses of the several clock signals are phased in accordance with the requirements of the processor. The pulse width and phasing of the several clock signals collectively determine the clock cycle time and clock frequency, and hence the operating speed of the processor.
In order to make the operating speeds of the known processors as high as possible, as is desirable, the clock signal pulse widths in those processors have been made to be as small as possible. However, such pulse widths have to be sufficiently large to meet the operating time requirements, and hence to match the operating speeds, of all of the timed portions which have their operations timed by those clock pulses. Those operating time requirements of the several timed portions of the usual processor cover a sizable range.
Because of the conditions just noted, it has become the practice to make the pulses of each clock signal in a processor to have a fixed, predetermined width which meets the operating time requirements of the slowest one of only those of the timed portions which that clock signal times. Due to the above-noted extent of the differences in operating speeds of the timed portions of the usual processor, this practice permits the pulse width for a given clock signal to be significantly smaller than that for another of the clock signals, and provides a desirable increase in processor operating speed. Such clock signals are referred to as being nonsymmetrical. An example of a processor including a multiphase clock generator which provides a set of nonsymmetrical clock signals is disclosed in the Raymond U.S. Pat. No. 4,037,090.
Although the known generator arrangements which provide nonsymmetrical clock signals give the desired increases in processor operating speed noted above, such arrangements have also been more complex than is often desired. Thus, a need exists for a nonsymmetrical clock generator of relatively simple form.
Additionally, in an effort to increase processor operating speeds as much as possible, the operating speeds of the timed portions of the known processors have been increased over the years. This has permitted corresponding reductions in clock pulse widths and clock cycle times which have resulted in significant increases in clock frequencies and processor operating speeds. Nevertheless, the operating speeds of the known processors are still not as high as is desired. The reason for this is that the operating speed of a processor of the known type is still, basically, dictated and limited, and hence degraded, by the operating time requirements of the slower or slowest ones of the timed portions.